Multiplierless Design of Very Large Constant Multiplications in Cryptography

This brief addresses the problem of implementing very large constant multiplications by a single variable under shift-adds architecture using minimum number adders/subtractors. Due to intrinsic complexity problem, we introduce an approximate algorithm, called TÕLL, which partitions constants into smaller ones. To reduce operations, TÕLL incorporates graph-based and common subexpression elimination methods proposed for design multiplications. It can also consider delay multiplierless defined in terms maximum operations series, i.e., adder-steps, while reducing operations. High-level experimental results show that adder-steps be reduced significantly with little overhead Gate-level indicate lead 36.6% reduction gate-level area respect multiplier, delay-aware optimization yield 48.3% achievable when compared area-aware optimization.